integrated circuit systems, inc. ICS93732 0578j?06/20/08 block diagram low cost ddr phase lock loop zero delay buffer pin configuration recommended application: ddr zero delay clock buffer product description/features: low skew, low jitter pll clock driver max frequency supported = 266mhz (ddr 533) i 2 c for functional and output control feedback pins for input to output synchronization spread spectrum tolerant inputs 3.3v tolerant clk_int input switching characteristics: cycle - cycle jitter (66mhz): <120ps cycle - cycle jitter (>100mhz): <65ps cycle - cycle jitter (>200mhz): <75ps output - output skew: <100ps duty cycle: 49.5% - 50.5% functionality s t u p n is t u p t u o e t a t s l l p d d v at n i _ k l ct k l cc k l ct t u o _ b f v 5 . 2 ) m o n ( llhl n o v 5 . 2 ) m o n ( hhlh n o fb_int fb_int clk_int clk_int sclk sclk sd sd a a t t a a control control logic logic fb_outt fb_outt ddrc0 ddrc0 pll pll ddrt0 ddrt0 ddrc1 ddrc1 ddrt1 ddrt1 ddrc2 ddrc2 ddrt2 ddrt2 ddrc3 ddrc3 ddrt3 ddrt3 ddrc4 ddrc4 ddrt4 ddrt4 ddrc5 ddrc5 ddrt5 ddrt5 ddrc0 ddrt0 ddrt1 ddrc1 ddrt3 ddrc3 ddrc4 ddrt4 ddrt2 ddrc2 vdd vdd vdd vdda ddrc5 ddrt5 gnd gnd gnd gnd sclk clk_int fb_outt fb_int sdata n/c n/c n/c 28-pin 209mil ssop
2 ICS93732 0578j?06/20/08 pin descriptions pin # pin name pin type description 1 ddrc0 out "complimentar y " clock of differential pair output. 2 ddrt0 out "true" clock of differential pair output. 3 vdd pwr power supply, nominal 2.5v 4 ddrt1 out "true" clock of differential pair output. 5 ddrc1 out "complimentary" clock of differential pair output. 6 gnd pwr ground pin. 7 sclk in clock pin of i2c circuitry 5v tolerant 8 clk_int in "true" reference clock input. 9 n/c n/c no connection. 10 vdda pwr 2.5v power for the pll core. 11 gnd pwr ground pin. 12 vdd pwr power suppl y , nominal 2.5v 13 ddrt2 out "true" clock of differential pair output. 14 ddrc2 out "complimentar y " clock of differential pair output. 15 gnd pwr ground pin. 16 ddrc3 out "complimentar y " clock of differential pair output. 17 ddrt3 out "true" clock of differential pair output. 18 n/c n/c no connection. 19 fb_out out feedback output, dedicated for external feedback. 20 fb_int in true single-ended feedback input, provides feedback signal to internal pll for synchronization with clk_int to eliminate phase error. 21 n/c n/c no connection. 22 sdata i/o data pin for i2c circuitry 5v tolerant 23 vdd pwr power supply, nominal 2.5v 24 ddrt4 out "true" clock of differential pair output. 25 ddrc4 out "complimentary" clock of differential pair output. 26 ddrt5 out "true" clock of differential pair output. 27 ddrc5 out "complimentar y " clock of differential pair output. 28 gnd pwr ground pin.
3 ICS93732 0578j?06/20/08 absolute maximum ratings supply voltage (vdd & avdd) . . . . . . . . . . -0.5v to 3.6v logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . gnd ?0.5 v to v dd +0.5 v ambient operating temperature . . . . . . . . . 0c to +85c case temperature . . . . . . . . . . . . . . . . . . . . 115c storage temperature . . . . . . . . . . . . . . . . . . ?65c to +150c stresses above those listed under absolute maximum ratings may cause permanent damage to the device. these ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect product reliability. electrical characteristics - input / supply / common output parameters t a = 0 - 70c; supply voltage av dd , v dd = 2.50v 0.20v (unless otherwise stated) parameter symbol conditions min typ max units r t = 120w, c l = 12 pf at 100mhz 236 300 r t = 120w, c l = 12 pf at 133mhz 263 300 i ddpd cl=0 pf 100 ma output high current i oh v dd = 2.5v, v out = 1v -48 -33 -29 ma output low current i ol v dd = 2.5v, v out = 1.2v 29 33 37 ma high impedance ouptut current v dd = min to max, i oh = -1ma 2 2.25 v v dd = 2.3v, i oh = -12ma 1.95 v dd = min to max, i oh = 1ma 0.05 0.1 v v dd = 2.3v, i oh = 12ma 0.3 0.4 output capacitance 1 c out v i = v dd or gnd 3 pf 1. guaranteed by design, not 100% tested in production. operating supply current i oz v dd = 2.7v, v out = v dd or gnd low-level output voltage v ol high-level output voltage ma 10 v oh ma i dd2.5 recommended operation conditions t a = 0 - 70c; supply voltage av dd , v dd = 2.50v 0.20v (unless otherwise stated) parameter symbol conditions min typ max units analog / core supply volta av dd 2.3 2.5 2.7 v input voltage level v in 22.53 v output differential pair crossing voltage 1.32 v v oc 66/100/133/166mhz, v dd =2.50v 1.23 1.25
4 ICS93732 0578j?06/20/08 notes: 1. refers to transition on noninverting output. 2. while the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. this is due to the formula: duty cycle=t wh /t c , where the cycle (t c ) decreases as the frequency goes up. timing requirements t a = 0 - 70c; supply voltage av dd , v dd = 2.50v (unless otherwise stated) parameter symbol conditions min typ max units operatin g clock frequenc y freq o p input volta g e level: 0-2.50v 22 340 mhz input clock dut y c y cle 1 d tin 40 50 60 % clock stabilization 1 t stab from vdd = 2.5v to 1% target frequency 100 s 1. guaranteed by design, not 100% tested in production. switching characteristics t a = 0 - 70c; supply voltage av dd , v dd = 2.50v 0.20v (unless otherwise stated) parameter symbol conditions min typ max units 66 mhz 100 120 100 / 125/ 133/167mhz 48 65 200/267mhz 47 75 phase erro r 1 t p e -150 150 ps output to output skew 1 t skew 20 100 ps 66 mhz to 100mhz 49.5 50 50.5 % 101mhz to 267 mhz 49 49.4 51 % rise time, fall time 4 t r , t f load=120 ? /14pf 579 950 ps ps t c-c duty cycle (sign ended) 1,3 dc cycle to cycle jitter 1,2
5 ICS93732 0578j?06/20/08 1. the ics clock generator is a slave/receiver, i 2 c component. it can read back the data stored in the latches for verification. read-back will support intel piix4 "block-read" protocol . 2. the data transfer rate supported by this clock generator is 100k bits/sec or less (standard mode) 3. the input is operating at 3.3v logic levels. 4. the data byte format is 8 bit bytes. 5. to simplify the clock generator i 2 c interface, the protocol is set to use only " block-writes " from the controller. the bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte has been transferred. the command code and byte count shown above must be sent, but the data is ignored for those two bytes. the data is loaded until a stop sequence is issued. 6. at power-on, all registers are set to a default condition, as shown. general i 2 c serial interface information the information in this section assumes familiarity with i 2 c programming. for more information, contact ics for an i 2 c programming application note. how to write: ? controller (host) sends a start bit. ? controller (host) sends the write address d4 (h) ? ics clock will acknowledge ? controller (host) sends a dummy command code ? ics clock will acknowledge ? controller (host) sends a dummy byte count ? ics clock will acknowledge ? controller (host) starts sending first byte (byte 0) through byte 6 ? ics clock will acknowledge each byte one at a time . ? controller (host) sends a stop bit how to read: ? controller (host) will send start bit. ? controller (host) sends the read address d5 (h) ? ics clock will acknowledge ? ics clock will send the byte count ? controller (host) acknowledges ? ics clock sends first byte (byte 0) through byte 6 ? controller (host) will need to acknowledge each byte ? controller (host) will send a stop bit notes: controller (host) ics (slave/receiver) start bit address d4 (h) ack dummy command code ack dummy byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack stop bit how to write: controller (host) ics (slave/receiver) start bit address d5 (h) ack byte count ack byte 0 ack byte 1 ack byte 2 ack byte 3 ack byte 4 ack byte 5 ack byte 6 ack stop bit how to read:
6 ICS93732 0578j?06/20/08 bytes 0 to 4 are reseved power up default = 1. this allows operation with main clock. pin # name 0 1 pwd bit 7 2, 1 ddr0(t&c) output control rw disable enable 1 bit 6 4, 5 ddr1(t&c) output control rw disable enable 1 bit 5 - - reserved x - - 1 bit 4 - - reserved x - - 1 bit 3 13, 14 ddr2(t&c) output control rw disable enable 1 bit 2 17, 16 ddr3(t&c) output control rw disable enable 1 bit 1 - - reserved x - - 1 bit 0 - - reserved x - - 1 note: pin # name 0 1 pwd bit 7 - - reserved x - - 0 bit 6 - - reserved x - - 0 bit 5 - - reserved x - - 0 bit 4 - - reserved x - - 1 bit 3 24, 25 ddr4(t&c) output control rw disable enable 1 bit 2 - - reserved x - - 1 bit 1 26, 27 ddr5(t&c) output control rw disable enable 1 bit 0 - - reserved x - - 1 note: control function affected pin byte 5 byte 6 pwd = power up default pwd = power up default type bit control type control function affected pin bit control
7 ICS93732 0578j?06/20/08 ordering information ICS93732 y flft seating plane seating plane a1 a a2 e -c- - c - b .10 (.004) c .10 (.004) c c l index area index area 12 1 2 n d e1 e 209 mil ssop min max min max a -- 2.00 -- .079 a1 0.05 -- .002 -- a2 1.65 1.85 .065 .073 b 0.22 0.38 .009 .015 c 0.09 0.25 .0035 .010 d e 7.40 8.20 .291 .323 e1 5.00 5.60 .197 .220 e l 0.55 0.95 .022 .037 n 0 8 0 8 v ariations min max min max 28 9.90 10.50 .390 .413 10-0033 symbol in millimeters in inches common dimensions common dimensions see variations see variations 0.65 basic 0.0256 basic reference doc.: jedec publication 95, mo-150 see variations see variations n d mm. d (inch) example: designation for tape and reel packaging rohs compliant package type f = ssop revision designator (will not correlate with datasheet revision) device type prefix ics = standard device ics xxxx y f lf t
8 ICS93732 0578j?06/20/08 revision history rev. issue date description page # i 5/18/2005 added lf ordering information to tssop package. 8 j 6/20/2008 removed tssop ordering information. -
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